标题： 针对阿秒级节点的线友好领域特定处理器的物理设计探索 显示英文标题

标题： Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes

摘要： 本文介绍了面向机器学习（ML）的领域专用处理器（DSIP）架构的物理设计探索，解决了先进埃格朗德时代技术中的互连效率挑战。 该设计通过利用专用存储结构和SIMD（单指令多数据）单元，强调了缩短线长和提高核心密度。 使用IMEC A10纳米片节点PDK合成了五个配置，并进行了评估。 关键的物理设计指标在各个配置之间以及与VWR2A（最先进的DSIP基准）进行了比较。 结果表明，我们的架构在所有配置中均实现了超过2倍的归一化线长降低和3倍以上的密度提升，且各项指标变化很小，使其成为下一代DSIP设计的有前景解决方案。 这些改进是在最小的人工布局干预下实现的，证明了该架构内在的物理效率以及低成本布线友好实现的潜力。 显示英文摘要

摘要： This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), addressing the challenges of interconnect efficiency in advanced Angstrom-era technologies. The design emphasizes reduced wire length and high core density by utilizing specialized memory structures and SIMD (Single Instruction, Multiple Data) units. Five configurations are synthesized and evaluated using the IMEC A10 nanosheet node PDK. Key physical design metrics are compared across configurations and against VWR2A, a state-of-the-art (SoA) DSIP baseline. Results show that our architecture achieves over 2x lower normalized wire length and more than 3x higher density than the SoA, with low variability in the metrics across all configurations, making it a promising solution for next-generation DSIP designs. These improvements are achieved with minimal manual layout intervention, demonstrating the architecture's intrinsic physical efficiency and potential for low-cost wire-friendly implementation.