标题： ATLAS：一种自监督的跨阶段网表功耗模型，用于细粒度基于时间的布局功耗分析 显示英文标题

标题： ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis

摘要： 在VLSI设计中，精确的功耗预测对于有效的功耗优化至关重要，尤其是在设计从门级网表转换到版图阶段时。然而，传统的精确功耗仿真需要耗时的后端处理和仿真步骤，这显著阻碍了设计优化。为了解决这个问题，我们提出了ATLAS，它可以预测任何新设计的基于时间的版图功耗。据我们所知，ATLAS是第一个同时支持基于时间的功耗仿真和通用跨设计功耗建模的工作。它通过提出一种针对电路功耗定制的新预训练和微调范式，实现了这种通用的基于时间的功耗建模。针对商业工具的每周期版图功耗，我们的ATLAS在没有任何版图信息的情况下，对时钟树、寄存器和组合功耗组的平均绝对百分比误差（MAPE）分别仅为0.58%、0.45%和5.12%。总体而言，整个设计总功耗的MAPE小于1%，并且工作负载的推理速度明显快于商业工具的标准流程。 显示英文摘要

摘要： Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, traditional accurate power simulation requires time-consuming back-end processing and simulation steps, which significantly impede design optimization. To address this, we propose ATLAS, which can predict the ultimate time-based layout power for any new design in the gate-level netlist. To the best of our knowledge, ATLAS is the first work that supports both time-based power simulation and general cross-design power modeling. It achieves such general time-based power modeling by proposing a new pre-training and fine-tuning paradigm customized for circuit power. Targeting golden per-cycle layout power from commercial tools, our ATLAS achieves the mean absolute percentage error (MAPE) of only 0.58%, 0.45%, and 5.12% for the clock tree, register, and combinational power groups, respectively, without any layout information. Overall, the MAPE for the total power of the entire design is <1%, and the inference speed of a workload is significantly faster than the standard flow of commercial tools.