标题： ListenToJESD204B：一种用于基于FPGA的超声采集系统的轻量级开源JESD204B IP核 显示英文标题

标题： ListenToJESD204B: A Lightweight Open-Source JESD204B IP Core for FPGA-Based Ultrasound Acquisition systems

摘要： 对超声系统中数百个紧密同步通道在数十 MSPS 下运行的需求超过了传统低电压差分信号链的带宽、引脚数和延迟。尽管 JESD204B 串行接口缓解了这些限制，但商业 FPGA IP 核心是专有的、昂贵的且资源密集型的。我们提出了 ListenToJESD204B，这是一个在宽松的 Solderpad 0.51 许可证下发布的开源接收器 IP 核心，适用于 AMD Xilinx Zynq UltraScale+ 设备。用可综合的 SystemVerilog 编写，该核心支持四个 GTH/GTY 通道，速率为 12.8 Gb/s，并提供周期精确的 AXI-Stream 数据以及确定性的 Subclass~1 延迟。它仅占用 107 个可配置逻辑块（约 437 个 LUT），与同类商业可用 IP 相比减少了 79%。一个模块化的数据路径，包括每通道弹性缓冲器、SYSREF 锁定的 LMFC 生成和可选的 LFSR 解扰，便于扩展到高通道数。我们通过与 Xilinx JESD204C IP 在 JESD204B 模式下的仿真以及使用 TI AFE58JD48 ADCs 的硬件验证了协议合规性。通过在两个 12.8 Gb/s 链路上连续传输 80 MSPS、16 位样本 30 分钟，未出现任何错误，验证了模块的稳定性。 显示英文摘要

摘要： The demand for hundreds of tightly synchronized channels operating at tens of MSPS in ultrasound systems exceeds conventional low-voltage differential signaling links' bandwidth, pin count, and latency. Although the JESD204B serial interface mitigates these limitations, commercial FPGA IP cores are proprietary, costly, and resource-intensive. We present ListenToJESD204B, an open-source receiver IP core released under a permissive Solderpad 0.51 license for AMD Xilinx Zynq UltraScale+ devices. Written in synthesizable SystemVerilog, the core supports four GTH/GTY lanes at 12.8 Gb/s and provides cycle-accurate AXI-Stream data alongside deterministic Subclass~1 latency. It occupies only 107 configurable logic blocks (approximately 437 LUTs), representing a 79\% reduction compared to comparable commercially available IP. A modular data path featuring per-lane elastic buffers, SYSREF-locked LMFC generation, and optional LFSR descrambling facilitates scaling to high lane counts. We verified protocol compliance through simulation against the Xilinx JESD204C IP in JESD204B mode and on hardware using TI AFE58JD48 ADCs. Block stability was verified by streaming 80 MSPS, 16-bit samples over two 12.8 Gb/s links for 30 minutes with no errors.