标题： GSIM：加速大规模设计的RTL仿真 显示英文标题

标题： GSIM: Accelerating RTL Simulation for Large-Scale Designs

摘要： 寄存器传输级（RTL）仿真在硬件设计的设计空间探索、验证、调试和初步性能评估中被广泛使用。 在各种RTL仿真方法中，软件仿真由于其灵活性、低成本和易于调试而被最常用。 然而，复杂设计的缓慢仿真已成为设计流程中的瓶颈。 在这项工作中，我们探讨了RTL仿真的计算开销来源，并将其归纳为四个因素。 为了优化这些因素，我们在超节点级别、节点级别和位级别提出了几种技术。 最后，我们将这些技术实现在一个新颖的RTL仿真器GSIM中。 GSIM成功地模拟了最先进的开源RISC-V处理器香山。 此外，与Verilator相比，GSIM在香山上启动Linux时可以实现7.34倍的速度提升，在运行Rocket的CoreMark时可以实现19.94倍的速度提升。 显示英文摘要

摘要： Register Transfer Level (RTL) simulation is widely used in design space exploration, verification, debugging, and preliminary performance evaluation for hardware design. Among various RTL simulation approaches, software simulation is the most commonly used due to its flexibility, low cost, and ease of debugging. However, the slow simulation of complex designs has become the bottleneck in design flow. In this work, we explore the sources of computation overhead of RTL simulation and conclude them into four factors. To optimize these factors, we propose several techniques at the supernode level, node level, and bit level. Finally, we implement these techniques in a novel RTL simulator GSIM. GSIM succeeds in simulating XiangShan, the state-of-the-art open-source RISC-V processor. Besides, compared to Verilator, GSIM can achieve speedup of 7.34x for booting Linux on XiangShan, and 19.94x for running CoreMark on Rocket.