标题： FlashVault：具有零面积开销的通用NAND自加密 显示英文标题

标题： FlashVault: Versatile In-NAND Self-Encryption with Zero Area Overhead

摘要： 我们提出FlashVault，这是一种嵌入式NAND自加密架构，它将可重构的密码引擎嵌入到最先进的4D V-NAND结构的未使用硅区中。 FlashVault不仅支持用于数据加密的分组密码，还支持用于数字签名的公钥和后量子算法，所有这些都在NAND闪存芯片内完成。 这种设计使得每个NAND芯片能够作为自包含的可信执行环境运行，而不会增加面积开销，同时消除了对芯片外加密的需求。 我们在寄存器传输级（RTL）实现了FlashVault，并进行了布局布线（P&R）以进行准确的功耗/面积评估。 我们的分析表明，功耗预算决定了每个NAND芯片中的密码引擎数量。 我们将这种架构选择集成到全系统仿真中，并在一系列密码算法上评估其性能。 我们的结果表明，FlashVault始终优于基于CPU的加密（1.46~3.45倍）和近核处理架构（1.02~2.01倍），证明了其作为满足监管标准和企业策略所施加的多样化密码需求的安全SSD架构的有效性。 显示英文摘要

摘要： We present FlashVault, an in-NAND self-encryption architecture that embeds a reconfigurable cryptographic engine into the unused silicon area of a state-of-the-art 4D V-NAND structure. FlashVault supports not only block ciphers for data encryption but also public-key and post-quantum algorithms for digital signatures, all within the NAND flash chip. This design enables each NAND chip to operate as a self-contained enclave without incurring area overhead, while eliminating the need for off-chip encryption. We implement FlashVault at the register-transfer level (RTL) and perform place-and-route (P&R) for accurate power/area evaluation. Our analysis shows that the power budget determines the number of cryptographic engines per NAND chip. We integrate this architectural choice into a full-system simulation and evaluate its performance on a wide range of cryptographic algorithms. Our results show that FlashVault consistently outperforms both CPU-based encryption (1.46~3.45x) and near-core processing architecture (1.02~2.01x), demonstrating its effectiveness as a secure SSD architecture that meets diverse cryptographic requirements imposed by regulatory standards and enterprise policies.