标题： 钉子：不是另一个针对Chisel生成的RTL的故障注入框架 显示英文标题

标题： Nail: Not Another Fault-Injection Framework for Chisel-generated RTL

摘要： 故障仿真和模拟是评估集成电路可靠性的关键技术，能够进行早期阶段的漏洞分析，并支持实施有效的缓解策略。 高级硬件描述语言如Chisel有助于在对设计进行最小修改的情况下快速开发复杂的故障场景。 然而，现有的基于Chisel的故障注入（FI）框架受到粗粒度、指令级控制的限制，限制了故障建模的精度。 本工作介绍了Nail，一个基于Chisel的开源FI框架，通过引入基于状态的故障克服了这些限制。 这种方法使故障场景依赖于特定的系统状态，而不仅仅依赖于指令级触发器，从而消除了对故障激活精确时间的要求。 为了实现更高的控制性，Nail允许用户在运行时通过软件任意修改内部触发状态。 为此，Nail自动生成一个软件接口，提供对仪器化设计的简单访问。 这使得在活跃的FI活动中可以微调故障参数——这一特性对于FPGA模拟尤其有益，因为综合过程耗时较长。 利用这些特性，Nail缩小了基于仿真的FI框架的高速度、基于软件的方法的易用性以及仿真中实现的控制性之间的差距。 我们通过在RISC-V处理器中建模一个有故障的通用寄存器来展示Nail的基于状态的FI和软件框架。 尽管这可能看起来很简单，但它需要依赖状态的FI，并且在没有对设计进行根本性更改之前是不可能实现的。 该方法在仿真和FPGA模拟中都得到了验证，其中添加Nail引入的资源开销不到1%。 显示英文摘要

摘要： Fault simulation and emulation are essential techniques for evaluating the dependability of integrated circuits, enabling early-stage vulnerability analysis and supporting the implementation of effective mitigation strategies. High-level hardware description languages such as Chisel facilitate the rapid development of complex fault scenarios with minimal modification to the design. However, existing Chisel-based fault injection (FI) frameworks are limited by coarse-grained, instruction-level controllability, restricting the precision of fault modeling. This work introduces Nail, a Chisel-based open-source FI framework that overcomes these limitations by introducing state-based faults. This approach enables fault scenarios that depend on specific system states, rather than solely on instruction-level triggers, thereby removing the need for precise timing of fault activation. For greater controllability, Nail allows users to arbitrarily modify internal trigger states via software at runtime. To support this, Nail automatically generates a software interface, offering straightforward access to the instrumented design. This enables fine-tuning of fault parameters during active FI campaigns - a feature particularly beneficial for FPGA emulation, where synthesis is time-consuming. Utilizing these features, Nail narrows the gap between the high speed of emulation-based FI frameworks, the usability of software-based approaches, and the controllability achieved in simulation. We demonstrate Nail's state-based FI and software framework by modeling a faulty general-purpose register in a RISC-V processor. Although this might appear straightforward, it requires state-dependent FI and was previously impossible without fundamental changes to the design. The approach was validated in both simulation and FPGA emulation, where the addition of Nail introduced less than 1% resource overhead.