标题： ARISE：自动化RISC-V指令集扩展 显示英文标题

标题： ARISE: Automating RISC-V Instruction Set Extension

摘要： RISC-V是一种可扩展的指令集架构，因其在嵌入式系统中的流行而日益增长。 然而，针对特定需求对其进行优化，需要大量的手动工作。 为了弥合软件和ISA之间的差距，提出了工具ARISE。 它根据由可扩展的度量标准集选择的汇编模式，自动产生RISC-V指令。 这些度量标准实现了代码大小和指令计数减少的优化目标，包括静态和动态情况。 使用ISA描述语言CoreDSL生成指令集扩展。 允许无缝嵌入到高级工具中，如可重定向编译器Seal5或指令集模拟器ETISS。 ARISE在Embench-Iot上平均使静态代码大小提高了1.48%，动态代码大小提高了3.84%，执行的指令数量减少了7.39%。 显示英文摘要

摘要： RISC-V is an extendable Instruction Set Architecture, growing in popularity for embedded systems. However, optimizing it to specific requirements, imposes a great deal of manual effort. To bridge the gap between software and ISA, the tool ARISE is presented. It automates the generation of RISC-V instructions based on assembly patterns, which are selected by an extendable set of metrics. These metrics implement the optimization goals of code size and instruction count reduction, both statically and dynamically. The instruction set extensions are generated using the ISA description language CoreDSL. Allowing seamless embedding in advanced tools such as the retargeting compiler Seal5 or the instruction set simulator ETISS. ARISE improves the static code size by 1.48% and the dynamic code size by 3.84%, as well as the number of instructions to be executed by 7.39% on average for Embench-Iot.