标题： XDMA：异构多加速器SoC中布局灵活数据传输的分布式可扩展DMA架构 显示英文标题

标题： XDMA: A Distributed, Extensible DMA Architecture for Layout-Flexible Data Movements in Heterogeneous Multi-Accelerator SoCs

摘要： 随着现代AI工作负载越来越多地依赖异构加速器，确保加速器内存之间的高带宽和布局灵活的数据移动已成为一个紧迫的挑战。 直接内存访问（DMA）引擎为数据移动提供了高带宽利用率，但通常仅在连续内存访问时最优，因此需要额外的软件循环来进行数据布局转换。 这反过来会导致过多的控制开销和未充分利用的片上互连。 为了克服这种低效问题，我们提出了XDMA，这是一种分布式且可扩展的DMA架构，能够在高链路利用率下实现布局灵活的数据移动。 我们引入了三个关键创新：(1) 一种作为XDMA前端的数据流引擎，用硬件地址生成器替代软件地址生成器；(2) 一种分布式DMA架构，最大化链路利用率并分离配置与数据传输；(3) XDMA的灵活插件，在数据传输过程中实现即时的数据操作。 XDMA在合成工作负载中比基于软件的实现具有高达151.2倍/8.2倍的链路利用率，并在实际应用中比现有最先进的DMA加速器平均快2.3倍。 我们的设计在现有最先进的DMA解决方案上仅增加<2%的面积开销，同时消耗系统功耗的17%。 XDMA证明了协同优化内存访问、布局转换和互连协议是释放异构多加速器SoC性能的关键。 显示英文摘要

摘要： As modern AI workloads increasingly rely on heterogeneous accelerators, ensuring high-bandwidth and layout-flexible data movements between accelerator memories has become a pressing challenge. Direct Memory Access (DMA) engines promise high bandwidth utilization for data movements but are typically optimal only for contiguous memory access, thus requiring additional software loops for data layout transformations. This, in turn, leads to excessive control overhead and underutilized on-chip interconnects. To overcome this inefficiency, we present XDMA, a distributed and extensible DMA architecture that enables layout-flexible data movements with high link utilization. We introduce three key innovations: (1) a data streaming engine as XDMA Frontend, replacing software address generators with hardware ones; (2) a distributed DMA architecture that maximizes link utilization and separates configuration from data transfer; (3) flexible plugins for XDMA enabling on-the-fly data manipulation during data transfers. XDMA demonstrates up to 151.2x/8.2x higher link utilization than software-based implementations in synthetic workloads and achieves 2.3x average speedup over accelerators with SoTA DMA in real-world applications. Our design incurs <2% area overhead over SoTA DMA solutions while consuming 17% of system power. XDMA proves that co-optimizing memory access, layout transformation, and interconnect protocols is key to unlocking heterogeneous multi-accelerator SoC performance.